台灣電機電子工程學會
Taiwan Institute of Electrical and Electronic Engineering
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2009 International Symposium on Physical Design
Marriott Mission Valley, San Diego, California, USA
March 29 - April 1, 2009
http://www.ispd.cc
Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE/CAS and
IEEE/CEDA
Additional support from Cadence, IBM Research, Sun Microsystems, SpringSoft,
Synopsys, and Tela Innovations
The International Symposium on Physical Design provides a high-quality forum
for the exchange of ideas on the physical layout design of VLSI systems. The
scope of this symposium includes all aspects of physical design, from
high-level interactions with logic synthesis, down to back-end performance
analysis and verification.
Each regular paper presentation runs 25 minutes, and each invited talk has
30 minutes. The ISPD'09 Best Paper Award nominees are marked with an
asterisk (*).
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Advance Program
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SUNDAY, MARCH 29
5:30 - 7:00 pm Evening Reception
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MONDAY, MARCH 30
8:30 - 9:30 am Welcome and Keynote Address
Host: Gi-Joon Nam (IBM Research)
(Keynote Talk) One Look into the Future of CMOS Chip Design
Carl J. Anderson (IBM)
9:30 - 10:00 am Morning break
10:00 - 11:45 am Session 1: Global Layout Planning
Chair: Cheng-Kok Koh (Purdue University)
(Invited Talk) Early Stage Analysis for Power Distribution Networks
Kai Wang, Aveek Sarkar, Norman Chang and Shen Lin (Apache Design Automation)
Post-Floorplanning Power/Ground Ring Synthesis for Multiple-Supply-Voltage
Designs
Wan-Ping Lee, Diana Marculescu and Yao-Wen Chang
Multi-voltage Floorplan Design with Optimal Voltage Assignment
Zaichen Qian and Evangeline Young
Robust Interconnect Communication Capacity Algorithm by Geometric
Programming
Jifeng Chen, Jin Sun and Janet Wang
11:45 - 1:30 pm Lunch
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1:30 - 3:10 pm Session 2: Physical Synthesis and Circuit Optimization
Chair: Lars Hagen (Cadence)
* A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage
Assignment
Yifang Liu and Jiang Hu
On Stress Aware Active Area Sizing, Gate Sizing, and Repeater Insertion
Ashutosh Chakraborty and David Z. Pan
Fast Buffering for Optimizing Worst Slack and Resource Consumption in
Repeater Trees
Christoph Bartoschek, Stephan Held, Dieter Rautenbach and Jens Vygen
On Improving Optimization Effectiveness in Interconnect-Driven Physical
Synthesis
Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin and
Mahesh Iyer
3:10 - 3:40 pm Afternoon break
3:40 - 5:40 am Session 3: Nanotechnology: CMOS and Beyond
Chair: Lei He (University of California at Los Angeles)
(Invited talk) Will 22nm be our Catch-22? Design and CAD Challenges
Ruchir Puri (IBM)
(Invited talk) New Strategies for Gridded Physical Design in 32nm
Technologies and Beyond
Stephen P. Kornachuk and Michael C. Smayling (Tela Innovations)
(Invited talk) Vertical Slit Transistor based Integrated Circuits (VeSTICs)
Paradigm
Wojciech Maly (Carnegie Mellon University)
(Invited talk) Graphene Based Transistors: Physics, Status and Future
Perspectives
Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar and S. Hadi Rasouli
(University of California at Santa Barbara)
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TUESDAY, MARCH 31
8:30 - 10:00 am Session 4: Analog Design: Tools and Methodologies
Chair: Vassilios Gerousis (Cadence)
(Invited talk) Accelerated Design of Analog, Mixed-Signal Circuits with
Titan
Anirudh Devgan (Magma Design Automation)
(Invited talk) Physical Design Methodology for Analog Circuits in a
System-on-a-Chip Environment
Eric Soenen (TSMC)
(Invited Talk) Constraint-driven Design - The Next Step Towards Analog
Design Automation
Goeran Jerke (Robert Bosch GmbH) and Jens Lienig (Dresden University of
Technology)
10:00 - 10:45 pm Morning break
10:45 - 12:00 pm: Session 5: Layout Optimization for FPGAs and Regular
Fabrics
Chair: Bill Halpin (Synopsys)
* Transistor-Level Layout of High-Density Regular Circuits
Yi-Wei Lin, Malgorzata Marek-Sadowska and Wojciech Maly
Physical Optimization for FPGAs Using Post-Placement Topology Rewriting
Val Pevzner, Andrew Kennings and Andy Fox
A Routing Approach to Reduce Glitches in Low Power FPGAs
Quang Dinh, Deming Chen and Martin D.F. Wong
12:00 - 1:30 pm Lunch
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1:30 - 3:10 am Session 6: Manufacturability and Yield Enhancement
Chair: Jiang Hu (Texas A&M University)
Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch
Minimization
Kun Yuan, Jae-Seok Yang and David Z. Pan
An Automatic Optical-Simulation-Based Lithography Hotspot Fix Flow for
Post-Route Optimization
Yang-Shan Tong, Chia-Wei Lin and Sao-Jie Chen
Redundant Via Insertion with Wire Bending
Kuang-Yao Lee, Shing-Tung Lin and Ting-Chi Wang
Wire Shaping is Practical
Hongbo Zhang, Liang Deng, Kai-Yuan (Kevin) Chao and Martin D.F. Wong
3:10 - 3:40 pm Afternoon break
3:40 - 5:05 pm Session 7: Clocking and the ISPD'09 Clock Synthesis Contest
Chair: Cliff Sze (IBM)
(Invited Talk) Industrial Clock Synthesis
Pei-Hsin Ho (Synopsys)
An Algorithm for Routing with Capacitance/Distance Constraints for Clock
Distribution in Microprocessors
Rupesh Shelar
(Invited Talk) ISPD'09 Clock Synthesis Contest Results
Cliff Sze (IBM)
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WEDNESDAY, APRIL 1
8:30 - 10:10 pm Session 8: Advances in Routing
Chair: Tong Gao (Synopsys)
Critical-Trunk-based Obstacle-Avoiding Rectilinear Steiner Tree Routings for
Delay and Slack Optimization
Yen-Hung Lin, Shu-Hsin Chang and Yih-Lang Li
Layer Assignment for Via Optimization in Multi-layer Global Routing
Tsung-Hsien Lee and Ting-Chi Wang
A Faster Approximation Scheme for Timing Driven Minimum Cost Layer
Assignment
Shiyan Hu, Zhuo Li and Charles J. Alpert
Diffusion-Driven Congestion Reduction for Substrate Topological Routing
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta and Xian-Long
Hong
10:10am - 10:40am Morning Break
10:40 - 12:00 pm Session 9: Post-Si Prediction and Debug
Chair: Li-C. Wang (University of California at Santa Barbara)
(Invited Talk) The Challenges of Correlating Silicon and Models in High
Variability CMOS Processes
Robert C. Aitken (ARM)
* Synthesizing a Representative Critical Path for Post-Silicon Delay
Prediction
Qunzeng Liu and Sachin S. Sapatnekar
A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations
Chien-Pang Lu, Mango C.-T. Chao, Chen-Hsing Lo and Chih-Wei Chang
12:00 - 12:15 pm Closing Remarks
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SYMPOSIUM REGISTRATION
Please register on-line at http://www.ispd.cc by March 8th, 2009 for the
early registration discount rates.
Registration Rates
ACM/IEEE Member: early $380, late $455
Non-Member: early $455, late $530
Student: early $170, late $220
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HOTEL ACCOMODATIONS AND TRAVEL
ISPD'09 will be held at the Marriott Mission Valley Hotel in San Diego,
California. The hotel is located in the downtown area of San Diego.
Marriott Mission Valley Hotel
Room Rate: $169/night
Reserve By: March 8, 2009
Registration code: ISPISPA (either on the web or calling)
Reservations may be made online at
http://www.marriott.com/hotels/travel/sanmv-san-diego-marriott-mission-valley .
Free internet access is available within the hotel rooms. Reserve early to
give yourself the best chance of getting a room.
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Symposium Organization
General Chair: Gi-Joon Nam / IBM Research
Past Chair: David Z. Pan / University of Texas at Austin
Steering Committee:
David Z. Pan / University of Texas at Austin (Chair)
Patrick Groeneveld / Magma
Patrick H. Madden / SUNY Binghamton
Malgorzata Marek-Sadowska / University of California at Santa Barbara
Ruchir Puri / IBM
Technical Program Chair: Prashant Saxena / Synopsys
Technical Program Committee:
Ameya Agnihotri / Magma
Yao-Wen Chang / NTU
Chris Chu / Iowa State U
Lars Hagen / Cadence
Jiang Hu / Texas A&M U
Andrew Kennings / U Waterloo
Cheng-Kok Koh /Purdue U
Jens Lienig / TU Dresden
Rob Mains / Sun
Igor Markov / U Michigan
David Newmark / AMD
Hidetoshi Onodera / Kyoto U
Rajendran Panda / Freescale
Yegna Parasuram / Mentor Graphics
Prashant Saxena / Synopsys
Ankur Srivastava / U Maryland
Cliff Sze / IBM
Martin D. F. Wong / U Illinois
Linda H. Wu / AtopTech
Hannah H. Yang / Intel
Evangeline F. Y. Young/ Chinese U of HK
Publication Chair: Yao-Wen Chang / National Taiwan University
Publicity Chair/Webmaster: Jiang Hu / Texas A&M University
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