台灣電機電子工程學會
Taiwan Institute of Electrical and Electronic Engineering
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Co-sponsored by ACM SIGDA and the IEEE Computer Society
The System Level Interconnect Prediction (SLIP) Workshop focuses on modeling and prediction of usable properties of optimized interconnect systems and their impact on system performance. Both theory and applications of interconnect prediction techniques are highlighted, with emphasis on applications to architectural and micro-architectural exploration, physical design, interconnect technology planning and communication networks. In addition to the presentation of state-of-the-art papers in these fields, invited talks and tutorials by leading researchers aim to encourage dialogue between the architecture, physical design, and interconnect technology communities.
SLIP 2009 will feature special sessions on System Level Interconnect Prediction for Emerging Technologies, with emphasis on (1) implications of emerging technologies (e.g., 3D integration, carbon nanotubes, quantum cellular automata) on system level interconnect planning and synthesis;
(2) synergies between estimation and analysis techniques for circuit interconnect systems and other large-scale networks arising in other context such as social web networks and systems biology.
**** Paper submission deadline: April 10, 2009 ****
SCOPE
* Statistical properties of complex interconnect systems:
- Techniques and calibrations for "Rentian" and "non-Rentian"
interconnect estimation
- A priori, on-line, and a posteriori estimation of interconnect design parameters (wire length, area, power, delay, etc.)
* Applications in system design:
- Interconnect parameter and yield estimation for use in architecture design and CAD
- Interconnect planning flows for specific objectives (e.g., low power, high performance) or target technologies (e.g., ASIC / SoC, FPGA, System-in-package, 3-D integration, molecular / nanoelectronics)
* Applications in technology evaluation:
- Interconnect technology prediction for long-term industry roadmap projections
- Early (predictive) evaluation of novel interconnect technologies in a system's context
- Architectural and micro-architectural effects of interconnect optimization approaches
Authors are invited to electronically submit papers of up to 8 pages in ACM proceedings format by following the instructions at https://www.easychair.org/login.cgi?conf=slip09 . Proposals for special sessions are also welcomed, and should be directed to the Technical Program Chair. The proceedings of SLIP 2009 will be published by ACM Press; we anticipate that a special issue of a major journal will be devoted to expanded versions of the best symposium papers. SLIP 2009 will be co-located with 46th ACM/IEEE Design Automation Conference (http://www.dac.com ). More details about SLIP 2009, including submission guidelines, travel funding sources, and travel information can be found online at: http://www.sliponline.org .
General Chair
Chung-Kuan Cheng
University of California, San Diego, USA
Technical Program Chair
Sherief Reda
Brown University, USA
Local Arrangements Chair
Andrew B. Kahng
University of California, San Diego, USA
Finance Chair
Janet Wang
University of Arizona, USA
Publications Chair
Hailong Yao
University of California, San Diego, USA
Publicity Chair
Kambiz Samadi
University of California, San Diego, USA
Program Committee Members
Mashiro Aoyagi
AIST, Japan
Yu (Kevin) Cao
Arizona State Univ. , USA
Deming Chen
UIUC , USA
Chris Chu
Iowa State Univ., USA
Joni Dambre
Ghent Univ., Belgium
Masanori Hashimoto
Osaka Univ., Japan
Andrew B. Kahng
UC San Diego, USA
Andrew Kennings
University of Waterloo, Canada
Jens Lienig
Dresden Univ. of Tech., Germany
John Lillis
UI Chicago, USA
Igor Markov
Univ. of Michigan, USA
David Z. Pan
UT Austin, USA
Sherief Reda
Brown University, USA
Dirk Stroobandt
Ghent Univ., Belgium
Cliff Sze
IBM Research, Austin, Texas
Janet Wang
Univ. of Arizona, USA
Payman Zarkesh-Ha
Univ. of New Mexico, USA
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